A lithography overlay process is used in a semiconductor manufacturing process to achieve layer to layer interconnections. In a wafer manufacturing process or an integrating process, based on characteristics of different circuit line widths, complex circuit elements are formed and stacked on a wafer by using different masks to perform lithography overlay processes. But in the lithography overlay process, steppers, the wafer, and a processing environment will cause a so-called overlay error, wherein the overlay error will cause a displacement error between two mask layers. Besides, with continually shrinking critical dimensions, larger and larger wafer sizes, and increased mask numbers, an accuracy of the lithography overlay needs higher and higher. When an overlay error exceeds an error tolerance, a displacement error resulting from the overlay error may cause open circuits or short circuits and make an interlayer design circuit become useless after an electrical testing, thereby reducing a product yield.
In conventional lithography overlay processes, a symmetrical compensation method is only provided to adjust parameters and thus reduce overlay errors. But for a semiconductor device, there is not only a symmetrical circuit region with a width equal to a length disposed on a wafer, but also an asymmetric circuit region with a width unequal to a length disposed on the wafer. Traditional symmetrical compensation method includes compensating an x-axis offset and an y-axis offset with the same parameter. However, the symmetrical compensation method is only applied in the lithography overlay process of the wafer having the symmetrical circuit region, wherein the symmetrical circuit region has the width equal to the length. So the traditional symmetrical compensation method cannot satisfy an accuracy requirement of the wafer having the asymmetrical circuit region after compensating, wherein the asymmetrical circuit region has the width unequal to the length. In other words, for the wafer having the asymmetrical circuit region, the traditional symmetrical compensation method including compensating the x-axis offset and the y-axis offset with the same parameter cannot reduce the overlay errors effectively.
In view of the aforementioned reasons, there is a need to provide a new compensation method to reduce overlay errors of a wafer having an asymmetry circuit region after processing with a lithography overlay process.